Fin field effect transistors (finFETs) may be incorporated into integrated circuitry. Each finFET includes a fin (a tall thin semiconductor member) extending generally perpendicularly from a substrate. The fin comprises a pair of opposing sidewalls, and gate material is provided along at least one of the sidewalls. The gate material is spaced from the sidewall by gate dielectric material. A pair of source/drain regions is provided within the fin, and a channel region extends between the source/drain regions. In operation, the gate is utilized to selectively control current flow within the channel region.
The finFETs may be utilized as access transistors in integrated memory arrays; such as, for example, dynamic random access memory (DRAM) arrays. In some applications the finFETs may be incorporated into crosshair memory cells. In such applications the source/drain regions are on a pair of upwardly-projecting pedestals, and the channel region is along a trough extending between the pedestals. A charge-storage device (for instance, a capacitor) is electrically coupled with one of the source/drain regions, and a digit line is electrically coupled with the other of the source/drain regions. The gate is beneath the source/drain regions, and extends along the trough comprising the channel region. Example finFET structures, and example crosshair memory cells, are described in U.S. Pat. No. 8,741,758, and U.S. patent publication numbers 2009/0237996 and 2011/0193157.
It is desired to develop improved finFET devices which are suitable for utilization in highly integrated applications, to develop improved architectures for incorporating finFET devices into highly integrated memory and/or other circuitries, and to develop improved methods for fabricating architectures comprising finFET devices.